The present invention relates to a clock recovery circuit in a synchronous receiver of a code division multiple access/direct sequence (CDMA/DS) communication system, and more particularly, to a process and circuit for extracting a stable clock signal by maintaining a constant input level in order to recover a clock signal from a received signal.
The code division multiple access (i.e., CDMA) system is one example of multiple access communication systems. A typical form of the code division multiple access system is a spread spectrum multiple access (SSMA). Generally, spread spectrum systems use modulation techniques to enable multiple access, or to increase immunity to noise and interference. Spread spectrum systems make use of a sequential noise-like signal structure, for example pseudo-noise codes, to spread the normally narrow and information signal over a relatively wide band of frequencies. With code division multiple access, all earth stations within the system may transit on the same frequency at the same time. A spread spectrum receiver correlates these signals in order to retrieve the original information signal from the desired earth transmitter station. In a code division multiple access system, a specific code such as a pseudo-noise code (a PN code called a chip code used that transmissions from different earth stations are separated through envelope encryption and description techniques with each earth station using an unique chip code), or perhaps a frequency hopping pattern (e.g., a form of code division multiple access where a digital code is used to continually change the frequency of the carrier, the total available bandwidth being partitioned into smaller frequency bands, and the total transmission time being subdivided into smaller time slots, thereby enabling transmission within one limited frequency band for only a short period of time followed by transmission upon a different limited frequency band, each earth station within the code division multiple access network being assigned a different frequency hopping pattern), is assigned to each user and the user has one code, or pattern, capable of separating information at a receiving circuit.
In a code division multiple access system, there are no restrictions upon time or bandwidth. Each earth station transmitter may transmit whenever it wishes and can use any or all of the bandwidth allocated in a particular satellite system or channel. The code division multiple access system is sometimes referred to as a spread-spectrum multiple access system because there are no limitations upon bandwidth; transmissions may be spread throughout the entire allocated bandwidth spectrum for every earth station. Transmissions are separated through envelope encryption and description techniques; that is, each earth station's transmissions are encoded with a unique binary word called a chip code. In order to receive a particular earth station's transmission, a receiver must know the chip code of that station. With an encoder in the transmitter, input data (which may be pulse code modulated encoded voice band signals of raw data) is multiplied by a unique chip code to provide a code phase shift key (a PSK) that modulates an intermediate frequency carrier which is up-converted to a radio frequency for transmission. At the receiver, the radio frequency is down converted to an intermediate frequency. From the intermediate frequency, a coherent phase shift key carrier is recovered and the chip code is acquired and used to synchronize the receiver's code generator. It is important to note that although the receiver already knows the chip code, the receiver must generate the chip code synchronized in time with the received code. The recovered synchronous chip code multiples the recovered PSK carrier and generates a PSK modulates signal that contains the PSK carrier and the chip code. The received intermediate signal that contains the chip code, the PSK carrier, and the data information is compared to the received intermediate frequency signal in a correlator which, in substance, compares the two signals, essentially by subtracting one signal having the recovered PSK carrier component and the chip code component from a second signal having the received PSK carrier component, chip code component and data component, in order to recover the data. As the name implies, the correlator operates upon analog signals by looking for a correlation (that is, a similarity) between the incoming coded signal and the recovered chip code. The chip code is multiplied by the data; the product is either an in-phase code or one that is 180.degree. out of phase with the chip code. The recovered synchronous chip code is compared in the correlator to the received signaling elements. If all of the recovered chips correlate, the correlator generates one output state; and if none of the chips correlate, a different output state. When a correlation occurs, a bit decision circuit (e.g., a threshold detector) generates a corresponding logic condition.
In comparison with any other multiple access communication systems, the CDMA system does not have a precise system capacity. That is, if the number of users increases, a signal-to-interference ratio is lowered, and the capacity of the system deteriorates gradually until a signal-to-noise ratio (SNR) is dropped to a critical value. On the other hand, the CDMA system has advantages in that a signal to be sent to a user is not easily decoded by others. Thus, maintenance of secure data transmission, which is difficult to accommodate in multiple access systems, is possible with a CDMA system. Furthermore, as earlier noted a CDMA system can be simultaneously used by many users.
In typical current designs for a conventional spread spectrum CDMA/DS receivers, a signal receiver from an antenna is amplified, and down-converted. The down-converted signal is amplified and the amplified signal is applied to automatic gain control (AGC) circuit. Since the automatic gain control circuit is coupled in the mainpath of the signal received from the antenna, it is difficult to process the signal received via the antenna to provide a multilevel signal. Moreover, since the clock recovery is performed using a general purpose amplifier subsequent to adjustment of the gain by the automatic gain control circuit, wideband, input dynamic range of the divider stages in the clock recovery stage is narrow. In short, the automatic gain control circuit as contemplated in current receiver designs, adversely limits receiving intensity and the dynamic range of the input signal.
A recent effort to improve the design of CDMA/DS synchronous communication systems is disclosed in U.S. Pat. No. 5,121,407 of Partyka et al. for SPREAD SPECTRUM COMMUNICATIONS SYSTEM. In this system, in order to overcome a short delay multipath phenomenon within a building or other structure, strong signals without the an automatic gain control circuit are transmitted by eliminating or reducing CW (continuous wave) jamming signals created by crystal based devices such as computers, terminals, etc. In this case, the effective dynamic range can be extended and the acquisition time reduced while the stability is lowered due to different clock recovery levels.